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Freescale Semiconductor Technical Data
Document Number: MC33887 Rev. 13.0, 10/2008
5.0 A H-Bridge with Load Current Feedback
The 33887 is a monolithic H-Bridge Power IC with a load current feedback feature making it ideal for closed-loop DC motor control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33887 is able to control inductive loads with continuous DC load currents up to 5.0 A, and with peak current active limiting between 5.2 A and 7.8 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 10 kHz. The load current feedback feature provides a proportional (1/ 375th of the load current) constant-current output suitable for monitoring by a microcontroller's A/D input. This feature facilitates the design of closed-loop torque/speed control as well as open load detection. A Fault Status output pin reports undervoltage, short circuit, and overtemperature conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge outputs to tri-state (exhibit high impedance). The 33887 is parametrically specified over a temperature range of -40C TA 125C and a voltage range of 5.0 V V+ 28 V. Operation with voltages up to 40 V with derating of the specifications. Features Fully specified operation 5.0 V to 28 V Limited operation with reduced performance up to 40 V 120 m RDS(ON) Typical H-Bridge MOSFETs TTL/CMOS Compatible Inputs PWM Frequencies up to 10 kHz Active Current Limiting (Regulation) Fault Status Reporting Sleep Mode with Current Draw 50 A (Inputs Floating or Set to Match Default Logic States) * Pb-Free Packaging Designated by Suffix Codes VW and EK * * * * * * * *
Device MC33887DH/R2 MC33887VW/R2 MC33887AVW/R2 MC33887PNB/R2 MC33887DWB/R2 MCZ33887EK/R2
33887
H-BRIDGE
DH SUFFIX VW SUFFIX (Pb-FREE) 98ASH70273A 20-PIN HSOP
PNB SUFFIX 98ASA10583D 36-PIN PQFN Bottom View DWB SUFFIX EK SUFFIX (Pb-FREE) 98ASA10506D 54-PIN SOICW-EP
ORDERING INFORMATION
Temperature Range (TA) Package
20 HSOP
-40C to 125C
36 PQFN 54 SOICW-EP
6.0 V V+
33887
CCP IN OUT OUT OUT OUT OUT A/D FS EN IN1 IN2 D1 D2 FB OUT2 PGND AGND MOTOR V+ OUT1
MCU
Figure 1. 33887 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007 - 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CCP VPWR
EN
CHARGE PUMP
8 A (EACH)
5.0 V REGULATOR
CURRENT LIMIT, OVERCURRENT SENSE & FEEDBACK CIRCUIT OUT1 GATE DRIVE OUT2
IN1 IN2 D1 D2 25 A CONTROL LOGIC
OVER TEMPERATURE UNDERVOLTAGE
FS FB
AGND
PGND
Figure 2. 33887 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Tab AGND FS IN1 V+ V+ OUT1 OUT1 FB PGND PGND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
EN IN2 D1 CCP V+ OUT2 OUT2 D2 PGND PGND
Tab Figure 3. 33887 Pin Connections Table 1. 33887 HSOP PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin 1 2 Pin Name AGND FS Formal Name Analog Ground Fault Status for H-Bridge Definition Low-current analog signal ground. Open drain active LOW Fault Status output requiring a pull-up resistor to 5.0 V. Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). Positive supply connections Output 1 of H-Bridge. Current sensing feedback output providing ground referenced 1/375th (0.00266) of H-Bridge high-side current. High-current power ground. Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. Output 2 of H-Bridge. External reservoir capacitor connection for internal charge pump capacitor. Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate.
3 4 , 5, 16 6, 7 8
IN1 V+ OUT1 FB
Logic Input Control 1 Positive Power Supply H-Bridge Output 1 Feedback for H-Bridge
9 - 12 13
PGND D2
Power Ground Disable 2
14 , 15 17 18
OUT2 CCP D1
H-Bridge Output 2 Charge Pump Capacitor Disable 1
19 20
IN2 EN
Logic Input Control 2 Enable
Tab/Pad
Thermal Interface
Exposed Pad Thermal Interface
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PIN CONNECTIONS
Transparent Top View of Package
36
35
34
33
32
31
30
29
CCP V+ V+ OUT2 OUT2 NC OUT2 OUT2
NC D1 IN2 EN V+ V+ NC AGND FS NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
28 27 26 25 24 23 22 21 20 19
NC D2 PGND PGND PGND PGND PGND PGND FB NC
Figure 4. 33887 Pin Connections Table 2. PQFN PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin 1, 7, 10, 16, 19, 28, 31 2 3 4 5, 6, 12, 13, 34, 35 8 9 11 14, 15, 17, 18 20 21- 26 27 29, 30, 32, 33 36 Pad Pin Name NC D1 IN2 EN V+ AGND FS IN1 OUT1 FB PGND D2 OUT2 CCP Thermal Interface Formal Name No Connect Disable 1 Logic Input Control 2 Enable Positive Power Supply Analog Ground Fault Status for H-Bridge Logic Input Control 1 H-Bridge Output 1 Feedback for H-Bridge Power Ground Disable 2 H-Bridge Output 2 Charge Pump Capacitor Exposed Pad Thermal Interface Definition No internal connection to this pin. Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Positive supply connections. Low-current analog signal ground. Open drain active LOW Fault Status output requiring a pull-up resistor to 5.0 V. Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). Output 1 of H-Bridge. Current feedback output providing ground referenced 1/375th ratio of H-Bridge high-side current. High-current power ground. Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. Output 2 of H-Bridge. External reservoir capacitor connection for internal charge pump capacitor. Exposed pad thermal interface for sinking heat from the device. Note: Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate.
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IN1 V+ V+ OUT1 OUT1 NC OUT1 OUT1
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
Transparent Top View of Package
PGND PGND PGND PGND NC NC NC D2 NC OUT2 OUT2 OUT2 OUT2 NC V+ V+ V+ V+ NC NC NC NC CCP D1 IN2 EN NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 .35 34 33 32 31 30 29 28
PGND PGND PGND PGND NC NC NC FB NC OUT1 OUT1 OUT1 OUT1 NC V+ V+ V+ V+ NC NC NC NC IN1 FS AGND NC NC
Figure 5. 33887 Pin Connections Table 3. SOICW-EP PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin 1- 4, 51- 54 5 - 7, 9, 14, 19 - 22, 27 - 29, 33 - 36, 41, 46, 48 - 50 8 Pin Name PGND NC Formal Name Power Ground No Connect High-current power ground. No internal connection to this pin. Definition
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. Output 2 of H-Bridge. Positive supply connections. External reservoir capacitor connection for internal charge pump capacitor. Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Low-current analog signal ground. Open drain active LOW Fault Status output requiring a pull-up resistor to 5.0 V. Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
10 - 13 15 - 18, 37 - 40 23
OUT2 V+ CCP
H-Bridge Output 2 Positive Power Supply Charge Pump Capacitor
24
D1
Disable 1
25 26
IN2 EN
Logic Input Control 2 Enable
30 31
AGND FS
Analog Ground Fault Status for H-Bridge
32
IN1
Logic Input Control 1
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PIN CONNECTIONS
Table 3. SOICW-EP PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin 42 - 45 47 Pin Name OUT1 FB Formal Name H-Bridge Output 1 Feedback for H-Bridge Output 1 of H-Bridge. Current feedback output providing ground referenced 1/375th ratio of H-Bridge high-side current. Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. Definition
Pad
Thermal Interface
Exposed Pad Thermal Interface
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating ELECTRICAL RATINGS Supply Voltage (1) Input Voltage
(2)
Symbol V+ VIN V FS IOUT
Value -0.3 to 40 - 0.3 to 7.0 -0.3 to 7.0 5.0
Unit V V V A V
FS Status Output (3) Continuous Current (4) DH Suffix HSOP ESD Voltage (5) Human Body Model Each Pin to AGND Each Pin to PGND Each Pin to V+ Each I/O to All Other I/Os Machine Model VW Suffix HSOP, SOICW-EP, and PQFN ESD Voltage Human Body Model Machine Model THERMAL RATINGS Storage Temperature Operating Temperature (6) Ambient Junction Peak Package Reflow Temperature During Reflow (7), (8)
(5)
VESD1 VESD1 VESD1 VESD1 VESD2 VESD1 VESD2 TSTG TA TJ TPPRT
1000 1500 2000 2000 200 V 2000 200
- 65 to 150 - 40 to 125 - 40 to 150 Note 8.
C C
C
Notes 1 Performance at voltages greater than 28V is degraded.See Electrical Performance Curves on page 18 and 19 for typical performance. Extended operation at higher voltages has not been fully characterized and may reduce the operational lifetime. 2 Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device. 3 Exceeding the pull-up resistor voltage on the open Drain FS pin may cause permanent damage to the device. 4 Continuous current capability so long as junction temperature is 150C. 5 ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 6 The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief nonrepetitive excursions of junction temperature above 150C can be tolerated as long as duration does not exceed 30 seconds maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.) Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
7 8.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted.
Rating Junction-to-Board (Bottom Exposed Pad Soldered to Board) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (13) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)
(14)
Symbol RJB
Value
Unit C/W
THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (9), (10), (11), (12) ~7.0 ~8.0 ~9.0 RJA ~ 41 ~ 50 ~ 62 RJMA ~ 18 ~ 21 ~ 23 RJC ~ 0.8 ~1.2 ~2.0 C/W C/W C/W
HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) Junction-to-Case (Exposed Pad) (15) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W)
Notes 9 The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. 10 Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RJB (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die temperature represents ~ 16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RJC-total must be less than 5.0 C/W for maximum load at 70C ambient. Module thermal design must be planned accordingly. 11 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 12 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 13 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 14 Per JEDEC JESD51-6 with the board horizontal. 15 Indicates the maximum thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V V+ 28 V and -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER SUPPLY Operating Voltage Range (16) Sleep State Supply Current IOUT = 0 A, VEN = 0 V Standby Supply Current IOUT = 0 A, VEN = 5.0 V Threshold Supply Voltage Switch-OFF Switch-ON Hysteresis CHARGE PUMP Charge Pump Voltage V+ = 5.0 V 8.0 V V+ 28 V CONTROL INPUTS Input Voltage (IN1, IN2, D1, D2) Threshold HIGH Threshold LOW Hysteresis Input Current (IN1, IN2, D1) VIN - 0.0 V Input Current (D2, EN) V D2 = 5.0 V IINP - 25 100 VIH VIL VHYS IINP - 200 - 80 - A 3.5 - 0.7 - - 1.0 - 1.4 - A V VCP - V+ 3.35 - - - - 20 V V+(THRES-OFF) V+(THRES-ON) V+(HYS) 4.15 4.5 150 4.4 4.75 - 4.65 5.0 - V V mV IQ (STANDBY) - - 20
(17)
Symbol
Min
Typ
Max
Unit
V+ IQ (SLEEP)
5.0
-
28
V A
-
25
50 mA
Notes 16 Specifications are characterized over the range of 5.0 V V+ 28 V. See See Electrical Performance Curves on page 18 and 19 and the See Functional Description on page 21 for information about operation outside of this range. 17 IQ (sleep) is with sleep mode function enabled.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V V+ 28 V and -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER SUPPLY POWER OUTPUTS (OUT1, OUT2) Output ON-Resistance (18) 5.0 V V+ 28 V, TJ = 25C 8.0 V V+ 28 V, TJ = 150C 5.0 V V+ 8.0 V, TJ = 150C Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) on Low-Side MOSFETs (19) High-Side Short Circuit Detection Threshold Low-Side Short Circuit Detection Threshold Leakage Current (20) VOUT = V+ VOUT = Ground Output MOSFET Body Diode Forward Voltage Drop IOUT = 3.0 A Overtemperature Shutdown Thermal Limit Hysteresis HIGH-SIDE CURRENT SENSE FEEDBACK Feedback Current I OUT = 0 mA I OUT = 500 mA I OUT = 1.5 A I OUT = 3.0 A I OUT = 6.0 A FAULT STATUS (21) Fault Status Leakage Current (22) V FS = 5.0 V Fault Status SET Voltage (23) I FS = 300 A Notes 18 19 20 21 22 23 V FS(LOW) - - 1.0 I FS(LEAK) - - 10 V A I FB - 1.07 3.6 7.2 14.4 - 1.33 4.0 8.0 16 600 1.68 4.62 9.24 18.48 A mA mA mA mA TLIM THYS 175 10 - - 225 30 VF - - 2.0 C ILIM ISCH ISCL IOUT(LEAK) - - 100 30 200 60 V RDS(ON) - - - 5.2 11 8.0 120 - - 6.5 - - - 225 300 7.8 - - A A A A m Symbol Min Typ Max Unit
Output-ON resistance as measured from output to V+ and ground. Active current limitation applies only for the low-side MOSFETs. Outputs switched OFF with D1 or D2. Fault Status output is an open Drain output requiring a pull-up resistor to 5.0 V. Fault Status Leakage Current is measured with Fault Status HIGH and not SET. Fault Status Set Voltage is measured with Fault Status LOW and SET with I FS = 300 A.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V V+ 28 V and -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic TIMING CHARACTERISTICS PWM Frequency (24) Maximum Switching Frequency During Active Current Limiting Output ON Delay (26) V+ = 14 V Output OFF Delay (26) V+ = 14 V ILIM Output Constant-OFF Time for Low-Side MOSFETs ILIM Blanking Time for Low-Side MOSFETs (29), (28) Output Rise and Fall Time (30) V+ = 14 V, IOUT = 3.0 A Disable Delay Time (31) Power-ON Delay Time
(32) (27) (28) (25)
Symbol
Min
Typ
Max
Unit
f PWM f MAX t D (ON)
- -
10 -
- 20
kHz kHz s
- t D (OFF) - , tA tB t F, t R 2.0 t D (DISABLE) t POD t WUD
(33)
-
18 s
- 20.5 16.5
18 26 21 s s s
15 12
5.0 - 1.0 1.0 -
8.0 8.0 5.0 5.0 - s ms ms ns
- - - 100
Wake-Up Delay Time (32) Output MOSFET Body Diode Reverse Recovery Time
tRR
Notes 24 The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See Typical Switching Waveforms, Figures 12 through 19, pp. 14-17. 25 The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces a constant-OFF-time pulse-width modulation of the output current. The output load's inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit. 26 Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 6, page 12. 27 ILIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge. 28 Load currents ramping up to the current regulation threshold become limited at the ILIM value. The short circuit currents possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF. See Figures 10 and 11, page 13. Operation in Current Limit mode may cause junction temperatures to rise. Junction temperatures above ~160C will cause the output current limit threshold to progressively "fold back", or decrease with temperature, until ~175C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this fold-back region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See Figure 9, page 12. 29 ILIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators my have time to act. 30 Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 8, page 12. 31 Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 7, page 12. 32 Parameter has been characterized but not production tested. 33 Parameter is guaranteed by design but not production tested.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
5. 0 50% 0 VPWR t D(ON) 90% 50% t D(OFF)
0 TIME
10%
Figure 6. Output Delay Time
5.0 V
0V
0
Figure 7. Disable Delay Time
VPWR 90% 10% 0 10%
tF
tR 90%
Figure 8. Output Switching Time
IILIM,ILIM, CURRENT (A) (A) MAX OUTPUT CURRENT
6.5 6.6
Operation within this region must be limited to nonrepetitive events not to exceed 30 seconds
4.0 2.5
Thermal Shutdown
150
160 175 T J, JUNCTION TEMPERATURE (o C)
Figure 9. Active Current Limiting Versus Temperature (Typical)
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
ILOAD, OUTPUT CURRENT (A)
>8A 6.5 Active Current Limiting on Low-Side MOSFET 0 IN1 or IN2 IN1 or IN2
Short Circuit Detection Threshold Typical Current Limit Threshold High Current Load Being Regulated via Constant-OFF-Time PWM Hard Short Detection and Latch-OFF Moderate Current Load
INn, LOGIC IN
[1] IN1 IN2
[0]
IN2 or IN1
IN2 or IN1
D1, LOGIC IN D2, LOGIC IN SF, LOGIC OUT
[1]
[0]
[1]
[0]
[1] Outputs [0]
Tri-Stated
Outputs Operation (per Input Control Condition) Time
Outputs Tri-Stated
Figure 10. Operating States
ILOAD, OUTPUT CURRENT (A) IOUT, CURRENT (A)
8.0 t on 6.5 ta a
IShort Circuit Detect Threshold Overcurrent Minimum Threshold SCL Short Circuit Detection Threshold tb b ta = Tristate Output OFF Time a = Output Constant-OFF Time ILIM Blanking Time ttb = Current Limit Blank Time b = Output Blanking Time Typical Current Typical PWM Load Limiting Waveform Current Limiting Waveform Hard short occurs. short Detection Hard Output Hard Short is detected during t b Short Latch-OFF and output is latched-off. TIME
0.0 5.0
Figure 11. Example Short Circuit Detection Detail on Low-Side MOSFET
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ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS
TYPICAL SWITCHING WAVEFORMS
Important For all plots, the following applies: * Ch2 = 2.0 A per division * LLOAD = 533 H @ 1.0 kHz * LLOAD = 530 H @ 10.0 kHz * RLOAD = 4.0
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=24 V
fPWM =1.0 kHz Duty Cycle=10%
Figure 12. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 10%
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=24 V
fPWM = 1.0 kHz Duty Cycle = 50%
Figure 13. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 50%
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=34 V
fPWM =1.0 kHz Duty Cycle=90%
Figure 14. Output Voltage and Current vs. Input Voltage at V+ = 34 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 90%, Showing Device in Current Limiting Mode
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=22 V
fPWM =1.0 kHz Duty Cycle=90%
Figure 15. Output Voltage and Current vs. Input Voltage at V+ = 22 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 90%
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ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=24 V
fPWM =10 kHz
Duty Cycle=50%
Figure 16. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 10 kHz, and Duty Cycle of 50%
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=24 V
fPWM =10 kHz
Duty Cycle=90%
Figure 17. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 10 kHz, and Duty Cycle of 90%
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ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=12 V
fPWM =20 kHz
Duty Cycle=50%
Figure 18. Output Voltage and Current vs. Input Voltage at V+ = 12 V, PMW Frequency of 20 kHz, and Duty Cycle of 50% for a Purely Resistive Load
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
V+=12 V
fPWM =20 kHz
Duty Cycle=90%
Figure 19. Output Voltage and Current vs. Input Voltage at V+ = 12 V, PMW Frequency of 20 kHz, and Duty Cycle of 90% for a Purely Resistive Load
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES

2KPV

9ROWV
Figure 20. Typical High-Side RDS(ON) Versus V+

2KPV 2+06

9ROWV 93:5
Figure 21. Typical Low-Side RDS(ON) Versus V+
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
2+06 0LOOLDPSHUHV

Figure 22. Typical Quiescent Supply Current Versus V+
9ROWV 93:5
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
Table 6. Truth Table The tri-state conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = LOW, H = HIGH, X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off).
Device State Input Conditions Fault Status Flag Output States
EN Forward Reverse Freewheeling Low Freewheeling High Disable 1 (D1) Disable 2 (D2) IN1 Disconnected IN2 Disconnected D1 Disconnected
D2 Disconnected
D1 L L L L H X L L Z X X X X X X
D2 H H H H X L H H X Z X X X X X
IN1 H L L H X X Z X X X X X X X X
IN2 L H L H X X X Z X X X X X X X
FS H H H H L L H H L L L L L H H
OUT1 H L L H Z Z H X Z Z Z Z Z Z Z
OUT2 L H L H Z Z X H Z Z Z Z Z Z Z
H H H H H H H H H H H
(35)
Undervoltage (34) Overtemperature Short Circuit (35) Sleep Mode EN EN Disconnected
H H L Z
Notes 34 In the case of an undervoltage condition, the outputs tri-state and the fault status is SET logic LOW. Upon undervoltage recovery, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 35 When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals and the fault status flag is SET logic LOW.
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Numerous protection and operational features (speed, torque, direction, dynamic braking, PWM control, and closedloop control), in addition to the 5.0 A current capability, make the 33887 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 33887 devices can be used to control bipolar stepper motors. The 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents.
FUNCTIONAL PIN DESCRIPTIONS POWER GROUND AND ANALOG GROUND (PGND AND AGND)
Power and analog ground pins should be connected together with a very low impedance connection. few milliamperes. Refer to Table 6, Truth Table, and STATIC ELECTRICAL CHARACTERISTICS table, page 9.
H-BRIDGE OUTPUT (OUT1 AND OUT2)
These pins are the outputs of the H-Bridge with integrated output MOSFET body diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The low-side MOSFETs have active current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) USED to detect currents that are higher than current limit is activated at each output activation to facilitate hard short detection (see Figure 11, page 13).
POSITIVE POWER SUPPLY (V+)
V+ pins are the power supply inputs to the device. All V+ pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. V+ pins have an undervoltage threshold. If the supply voltage drops below a V+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is SET and the Fault Status pin voltage switched to a logic LOW. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic HIGH. As V+ increases in value above 28 V, the charge pump performance begins to degrade. At +40 V, the charge pump is effectively non-functional. Operation at this high voltage level will result in the output FETs not being enhanced when turned on. This means that the voltage on the output will be VOUT = (V+) - VGS. This increased voltage drop under load will produce a higher power dissipation.
Charge Pump Capacitor (CCP)
A filter capacitor (up to 33 nF) can be connected from the charge pump output pin and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency.
ENABLE (EN)
The EN pin is used to place the device in a sleep mode so as to consume very low currents. When the EN pin voltage is a logic LOW state, the device is in the sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor maintains the device in sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected.
FAULT STATUS (FS)
The FS pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to 5.0 V. Refer to Table 6, Truth Table, page 20.
LOGIC INPUT CONTROL AND DISABLE (IN1, IN2, D1, AND D2)
These pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the circuitry is fully operational and the supply IQ (standby) current is reduced to a
FEEDBACK FOR H-BRIDGE (FB)
The 33887 has a feedback output (FB) for "real time" monitoring of H-Bridge high-side current to facilitate closedloop operation for motor speed and torque control. The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this pin. Through an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can "read" the current proportional
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTIONS
voltage with its analog-to-digital converter (ADC). This is intended to provide the user with motor current feedback for motor torque control. The resistance range for the linear operation of the FB pin is 100 < RFB < 200 .
If PWM-ing is implemented using the disable pin inputs (either D1 or D2), a small filter capacitor (1.0 F or less) may be required in parallel with the external resistor to ground for fast spike suppression.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33887 Simplified Internal Block Diagram shown in Figure 2, page 2, is a fully protected monolithic H-Bridge with Enable, Fault Status reporting, and High-Side current sense feedback to accommodate closed-loop PWM control. For a DC motor to run, the input conditions need be as follows: Enable input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS flag cleared (logic HIGH), one IN logic LOW and the other IN logic HIGH (to define output polarity). The 33887 can execute dynamic braking by simultaneously turning on either both high-side MOSFETs or both low-side MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic LOW. The 33887 outputs are capable of providing a continuous DC load current of 5.0 A from a 28 V V+ source. An internal charge pump supports PWM frequencies to 10 kHz. An external pull-up resistor is required at the FS pin for fault status reporting. The 33887 has an analog feedback (current mirror) output pin (the FB pin) that provides a constantcurrent source ratioed to the active high-side MOSFET. This can be used to provide "real time" monitoring of load current to facilitate closed-loop operation for motor speed/torque control. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) provide the means to force the H-Bridge outputs to a high-impedance state (all H-Bridge switches OFF). An EN pin controls an enable function that allows the 33887 to be placed in a power-conserving sleep mode. The 33887 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latchOFF, and overtemperature latch-OFF. An undervoltage shutdown, output short-circuit latch-OFF, or overtemperature latch-OFF fault condition will cause the outputs to turn OFF (i.e., become high impedance or tri-stated) and the fault output flag to be set LOW. Either of the Disable inputs or V+ must be "toggled" to clear the fault flag. Active current limiting is accomplished by a constant OFFtime PWM method employing active current limiting threshold triggering. The active current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold. This means the active current limiting threshold is "ramped down" as the junction temperature increases above 160C, until at 175C the current will have been decreased to about 4.0 A. Above 175C, the overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to remain in operation for 30 seconds at junction temperatures above 150C for nonrepetitive unexpected loads.
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES SHORT CIRCUIT PROTECTION
If an output short circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and the fault status output flag is SET logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the D2 input changes from logic LOW to logic HIGH, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic HIGH state. The output stage will always switch into the mode defined by the input pins (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature range. and overtemperature shutdown occurs (see Figure 9, page 12). This feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160C.
Output Avalanche Protection
An inductive fly-back event, namely when the outputs are suddenly disabled and V+ is lost, could result in electrical overstress of the drivers. To prevent this the V+ input to the 33887 should not exceed the maximum rating during a flyback condition. This may be done with either a zener clamp and/or an appropriately valued input capacitor with sufficiently low ESR.
ACTIVE CURRENT LIMITING
The maximum current flow under normal operating conditions is internally limited to ILIM (5.2 A to 7.8 A). When the maximum current value is reached, the output stages are tri-stated for a fixed time (t a) of 20 s typical. Depending on the time constant associated with the load characteristics, the current decreases during the tri-state duration until the next output ON cycle occurs (see Figures 11 and 14, page 13 and page 15, respectively). The current limiting threshold value is dependent upon the device junction temperature. When -40C TJ 160C, ILIM is between 5.2 A to 7.8 A. When TJ exceeds 160C, the ILIM current decreases linearly down to 4.0 A typical at 175C. Above 175C the device overtemperature circuit detects TLIM
OVERTEMPERATURE SHUTDOWN AND HYSTERESIS
If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag is SET to logic LOW. To reset from this condition, D1 must change from logic HIGH to logic LOW, or D2 must change from logic LOW to logic HIGH. When reset, the output stage switches ON again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. Note Resetting from the fault condition will clear the fault status flag.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 23 shows a typical application schematic. For precision high-current applications in harsh, noisy environments, the V+ by-pass capacitor may need to be substantially larger.
DC MOTOR V+
33887
AGND V+ CCP
33 nF
+
47 F
OUT1 FB
OUT2 EN D2 D1 FS
+
1.0 F
100
PGND
IN1 IN2
FB IN2 IN1 FS D1 D2 EN
Figure 23. 33887 Typical Application Schematic
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PACKAGING SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 33887 packages are designed for thermal performance. The significant feature of these packages is the exposed pad on which the power die is soldered. When soldered to a PCB, this pad provides a path for heat flow to the ambient environment. The more copper area and thickness on the PCB, the better the power dissipation and transient behavior will be. Example Characterization on a double-sided PCB: bottom side area of copper is 7.8 cm2; top surface is 2.7 cm2 (see Figure ); grid array of 24 vias 0.3 mm in diameter .
Top Side
Bottom Side
Figure 24. PCB Test Layout
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PACKAGING PACKAGING DIMENSIONS
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A drawing number below
DH SUFFIX VW SUFFIX 20-PIN HSOP PLASTIC PACKAGE 98ASH70273A ISSUE E
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PACKAGING PACKAGING DIMENSIONS
DH SUFFIX VW SUFFIX 20-PIN HSOP PLASTIC PACKAGE 98ASH70273A ISSUE E
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PACKAGING PACKAGING DIMENSIONS
PNB (Pb-FREE) SUFFIX 36-PIN PQFN Pb-Free PACKAGE 98ASA10583D ISSUE C
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PACKAGING PACKAGING DIMENSIONS
PNB (Pb-FREE) SUFFIX 36-PIN PQFN Pb-Free PACKAGE 98ASA10583D ISSUE C
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PACKAGING PACKAGING DIMENSIONS
DWB SUFFIX EK SUFFIX (PB-FREE) 54-PIN SOICW EXPOSED PAD PLASTIC PACKAGE 98ASA10506D ISSUE C
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PACKAGING PACKAGING DIMENSIONS
DWB SUFFIX EK SUFFIX (PB-FREE) 54-PIN SOICW EXPOSED PAD PLASTIC PACKAGE 98ASA10506D ISSUE C
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33887DH
THERMAL ADDENDUM (REV 2.0)
Introduction This thermal addendum is provided as a supplement to the MC33887 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the data sheet. Packaging and Thermal Considerations The MC33887 is offered in a 20 pin HSOP exposed pad, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RJA). TJ
=
20-PIN HSOP-EP
DH SUFFIX 98ASH70273A 20-PIN HSOP-EP
RJA
.
P Note For package dimensions, refer to the 33887 device data sheet.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an applicationspecific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 7. Thermal Performance Comparison [C/W] 20 6.0 52 1.0
Thermal Resistance RJA(1),(2) RJB (2),(3) RJA (1), (4) RJC (5)
NOTES:
1.0 1.0 0.2 0.2 * All measurements are in millimeters Soldermast openings Thermal vias connected to top buried plane
1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4.Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated
20 Terminal HSOP-EP 1.27 mm Pitch 16.0 mm x 11.0 mm Body 12.2 mm x 6.9 mm Exposed Pad
Figure 25. Thermal Land Pattern for Direct Thermal Attachment According to JESD51-5
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
A
Tab AGND FS IN1 V+ V+ OUT1 OUT1 FB PGND PGND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
EN IN2 D1 CCP V+ OUT2 OUT2 D2 PGND PGND
Tab 33887 Pin Connections
20-Pin HSOP-EP 1.27 mm Pitch 16.0 mm x 11.0 mm Body 12.2 mm x 6.9 mm Exposed Pad
Figure 26. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat spreading areas on board surface Natural convection, still air
RJS
Table 8.
Thermal Resistance Performance
Area A (mm2) C/W
Thermal Resistance
RJA
0.0 300 600 0.0 300 600
52 36 32
Outline:
Area A: Ambient Conditions:
10 7.0 6.0
RJA is the thermal resistance between die junction and ambient air. RJS is the thermal resistance between die junction and the
reference location on the board surface near a center lead of the package (see Figure 26).
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
60
Thermal Resistance [C/W]
50 40 30 20
x
10 0
RJA
0
300 Heat spreading area A [mm]
600
Figure 27. Device on Thermal Test Board RJA
100 Thermal Resistance [C/W]
10
1
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s]
Figure 28. Transient Thermal Resistance RJA Device on Thermal Test Board Area A = 600 (mm2)
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION
10.0 11.0
7/2005 11/2006
12.0
1/2007
* Added Thermal Addendum & Converted to Freescale format, Revised PQFN drawing, made several minor spelling correction. Added 33887A * Updated Ordering information block with new epp information * Changed the supply/ operating voltage from 40 V to 28 V * Updated all package drawings to the current revision * Adjusted to match device performance characteristics * Updated the document to the prevailing Freescale form and style * Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 7. * Added note (8) * Added MCZ33887EK/R2 to the Ordering Information on Page 1 * Removed the 33887A from the data sheet and deleted Product Variation section now that is no longer needed. * Changed the third paragraph of the introduction on page 1 * Altered feature number 1 on page 1 * Added feature number 2 on page 1 * Changed Maximum Supply Voltage (1) to 0.3 to 40 V * Added note (1) * Changed note (16) * Added a third paragraph to Positive Power Supply (V+) on page 21 * Replaced Figure 20, Figure 21, and Figure 22 with updated information. * Added Part Number MC33887AVW/R2 to Ordering Information Table on page 1.
13.0
10/2008
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How to Reach Us:
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MC33887 Rev. 13.0 10/2008

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